1. Field of the Invention
The present invention relates to a multiple feedback loop ring oscillator with a high oscillation frequency and its delay cells.
2. Description of the Prior Art
In an optical communication using Asynchronous Transfer Mode (abbreviated as "ATM"), a transmitter sends serial data without timing information, i.e., clocks, and a receiver restores clocks from the received serial data, thereby obtains data synchronized the restored clocks. It is called a clock recovery circuit, the Phase-Locked Loop (abbreviated as "PLL") often used for this purpose. A high speed clock recovery circuit is needed and an oscillator has to be operated in high speed because high speed communication is more and more needed for a transmission and reception of more data in a proposed time.
PLL is widely used in the clock recovery circuit, a frequency synthesizer, a clock generator and a clock synchronization apparatus for a microprocessor. A controlled oscillator is a main part of a PLL, and it is classified into a voltage-controlled oscillator (abbreviated as "VCO") and a current-controlled oscillator (abbreviated as "CCO") in accordance-with oscillation frequency control methods. For a voltage-controlled oscillator an oscillation frequency is controlled by voltage and for a current-controlled oscillator it is controlled by current.
Both a voltage-controlled oscillator and a current-controlled oscillator have only one difference that voltage control an oscillation frequency or current from a voltage-to-current converter do it, so we'll call them VCO shortly from now onwards.
VCO implemented by integrated circuits is a ring oscillator, a relaxation oscillator and an LC oscillator. Important characteristic variables of VCO are jitter which are measured output vibration on a time domain, removal characteristics of power and substrate noise, and tuning ranges which present variable ranges of oscillation frequency followed by controlled voltage. The ring oscillator and the relaxation oscillator have an advantage that they can be implemented easily and have a wide tuning range. On the contrary, they have bad noise characteristics. In the LC oscillator, it shows good noise characteristics but it has narrow tuning ranges.
To obtain a high oscillation frequency in the ring oscillator, we can consider three points of view such as. Processes, delay cells and a structure of the ring oscillator. In a view point of processes, devices which have to operate in a high speed such as an oscillator or a mixer in a PLL in a waveband over a Gigahertz waveband can be manufactured by high speed processes like GaAs or bipolar. But such processes are expensive and have a low density, so it is more preferable to use Complementary Metal Oxide Semiconductor (abbreviated as "CMOS") processes for a high density and low cost. In CMOS processes, an operating speed of transistors is low compared to other processes, so when using CMOS process new design techniques are needed to obtain a high speed.
The oscillation frequency of oscillator depends upon the magnitude of output swing. Oscillation frequency becomes low in case of large output swing because more time that charge and discharge a load capacitance is needed comparing with small output swing. So in a view point of delay cells to obtain a high oscillation frequency, we have to constrain properly the output swing. For a same current because the more output impedance increases, the more output swing increases, we can decrease a load resistor of a delay cell to decrease output swing.
Transistors operated in triode region have much smaller output resistance value than those operated in saturation region do, thus the delay cell using transistors operated in triode region as its load can operate in a high speed because of a small output swing.
In the method using triode transistor as a load, the load is always on a triode region in the all-oscillation region of a ring oscillator, so an oscillation frequency is proportioned to a control voltage or current, and Replica Biasing methods which control indirectly ring oscillator's output using delay cells similar with a ring oscillator is used. This method can correctly control output swing, although it has a disadvantage that the power noise characteristic is bad because an output is connected to a power line directly through a small impedance triode transistor.
The other method to reduce output swing is a clamping of output voltage by using diodes. If we connect a gate and a drain of transistor, we can use it as a diode because the transistor is in a saturation region. If a diode turns on, the voltage of both terminals of a diode is proportional to the square root of a current, and a voltage dropping of diode is small, so it can be used as a voltage clamping which fixes an output voltage to a specific voltage.
As described above, in the conventional method which reduces output swing through a clamping of output voltage by using a diode, the output is directly connected to a power or a ground line through a transistor operated as a diode. Also in this case, because of the diode with a small impedance it has a disadvantage that the power sensitivity is high and the power noise characteristic is bad.
The ring oscillator is comprised of a negative feedback loop in a DC state. It oscillates if a loop gain is larger than `1` in the frequency that the total phase delay of a ring loop becomes 360 degrees. It is needed odd numbered stages to compose a negative feedback loop in the single-ended ring oscillator, however in the differential structured ring oscillator a negative feedback loop can be composed of even numbered stages.
The oscillation frequency, 1/(2NTd), is given inversely proportional to the delay time of a unit delay cell and the number of stages composed ring when the delay of the unit delay cell is Td and the number of stages is N. Therefore in a view point of the structure of the ring oscillator, the simplest method that increases the oscillation frequency is to reduce the number of stages of ring oscillator. However the fewer stages of ring oscillator are reduced, the more a minimum gain and a phase delay requested at a delay cell of each stage are increased for an oscillation. For example, in 4 stages ring oscillator the minimum gain and phase delay of each stage for an oscillation are each square root 2 and 90 degrees, but in 3 stages ring oscillator they are each 2 and 120 degrees.
The fewer the number of stages of ring oscillator is reduced, the more difficult phase delay conditions are satisfied among oscillation conditions such as a minimum gain, a phase delay, and so on. The phase delay has to be 180 degrees in case of 2 stages ring oscillator, and 360 degrees in case of 1 stage ring oscillator at each stage. One-stage amplifier is used as the delay cell of ring oscillator for the high oscillation frequency. However the delay cell with only simple one-stage amplifier is of no use in case of the ring oscillator less than 2 stages, because the maximum phase delay of one-stage amplifier is 180 degrees in an infinite frequency.
Therefore, in case of the ring oscillator less than 2 stages, we have to add phase delay factors such as capacitors or increase the phase delay of a delay cell using a positive feedback. In case of CMOS circuits, the oscillation frequency of the ring oscillator less than 2 stages becomes lower and more unstable than that of 3 stages ring oscillator because of the loading effect of added circuits for the purpose of the above method, so in CMOS processes we make a ring oscillator with more than 3 stages.
Data are transmitted in the serial form without clock signals in serial data communications. The receiver restores clock signals from pulse signals received continuously per given times of a unit bit period, and it revives data by synchronizing to the restored clocks. Jitter, the state that restored clocks vibrate continuously, has to be minimized in order that error rates of revived data are satisfied with given specifications.
In the conventional methods, the passive resonator which is tuned to known date rates is used to restore clocks, more particularly, surface acoustic wave (abbreviated as "SAW") filter is often used in the data rates more than 1 Gb/s. As described above, the method that restore clocks using the passive resonator with high Q has an advantage that jitter of restored clocks is small, however it has a disadvantage that a power consumption is high in order that it operates the resonator outside of a chip that has low impedance, and the delay time outside of a chip must be operated manually in order that it strobes optimum clocks in a data reviver.
However the method using PLL can solve above problems. In PLL all signals are operated inside of a chip, outside factors such as inductor or varactor in order to tuning VCO are not needed. Also because clocks can be restored from data existed on the whole frequency region of VCO, the drift of clocks caused by the variation of a temperature and a power line can be assimilated, and because a clock phase is fixed to an exact base signal such as crystal oscillator, it strobes optimally in a data reviving period.
High speed VCO is needed in order that high speed PLL is implemented.
In case of VCO which has no tuning elements with high Q outside the chip, it has many phase noises and jitter is caused in a restored clock, because of the external noise source such as a power noise and the noise of active elements such as a flicker noise of field effect transistor (abbreviated as "FET"), therefore, it is needed the method which can reduce noises. High speed VCO is needed in order that high speed PLL is implemented. As described above, there are such methods to implement high speed VCO; One is the method that uses high speed processes, another is the method that constrains output swing using replica biasing or diode clamping, the other is the method that reduces stages of a ring oscillator.
In a view point of a structure of a ring oscillator, to obtain high oscillation frequency of a ring oscillator, except the method which simply reduces stages of a ring oscillator, two conventional methods which restructure a ring oscillator for the purpose of high oscillation frequency as follows. one is the Pseudo One-Stage Ring Oscillator whose oscillation frequency is same as that of a 1 stage ring oscillator in a 3 stage ring oscillator, the other is the Frequency Quadrupling Ring Oscillator which can obtain 4 times oscillation frequency, more specifically, there is 90 degrees difference between In-phase and Quadrature-phase and In-phase signal multiplied by Quadrature-phase signal through mixer produecs 2 signals in mutual quadrature state, so the 2 signals in mutual quadrature state produce 4 times oscillation frequency by multiplying each other.
FIG. 1A is a circuit diagram of a conventional 1 stage ring oscillator and FIG. 1B is a output waveform of a conventional 1 stage ring oscillator.
The conventional circuit and waveform of pseudo 1 stage ring oscillator will be described below in detail with reference to FIGS. 1A and 1B.
The conventional circuit of pseudo 1 stage ring oscillator comprises inverter delay cells (111, 121, 131) which construct 3 stages ring oscillator, 3 trans-conductance amplifiers (112, 122, 132) which transfer a voltage input to a current output and a load resistor (141). Output currents of 3 trans-conductance amplifiers (112, 122, 132) are each I1, I2 and I3. We will call the output current which flows in the direction of the arrow in FIG. 1A "Sinking", when the input of trans-conductance amplifier is increasing. Also we will call the output current which flows in the opposite direction of the arrow in FIG. 1A "Sourcing", when the input of transconductance amplifier is decreasing.
Now, it is shown an operating mechanism of the circuit. We will simply call trans-conductance amplifiers in FIG. 1A amplifiers. Voltages at output nodes (113, 123, 133, 142) are V1, V2, V3 and V4. Because the circuit is a 3 stages ring oscillator, waveforms of output voltages at each nodes of oscillator, V1, V2 and V3 are shown in FIG. 1B. Because amplifiers (112, 122) are in a high state when the output voltage of node (113), V1 is increasing, output currents of amplifiers (112, 122), I1 and I2 are "Sinking", the output current of an amplifier (132), I3 is "Sourcing" and the voltage of the node (142), V4 becomes low. When the output V2 of oscillator becomes low after Td unit delay time of oscillator, V4 becomes high because the output current of amplifier (122), I2 is changed from "Sinking" to "Sourcing".
When the output voltage V3 becomes high after another period, V4 becomes low because of the same reason. As the above operation, after one period in the ring oscillator, the output voltage V4 is same as shown in FIG. 1B, then the frequency of V4 is 1/2Td, which is same as the oscillation frequency of 1 stage ring oscillator. It is assumed output voltages shown in FIG. 1B to be ideal digital outputs, however real output voltages V1, V2 and V3 of high speed ring oscillator are nearly sinusoidal waves, have same amplitude and have phase difference of 120 degrees each other. Therefore, output currents of amplifier, I1, I2 and I3 are almost sinusoidal waves, have same amplitude and have phase difference of 120 degrees each other. The sum of three complete sinusoidal signals which have phase difference of 120 degrees each other is `0`. Hence the output voltage V4 has no change only DC value, because output currents I1, I2 and I3 are complete sinusoidal waves and the sum of this three currents at load resistor (141) is `0` if waves of each output nodes (113, 123, 133) shown in FIG. 1A are complete sinusoidal waves.
However, real delay cells and amplifiers are nonlinear, so harmonics factors exist in outputs. If delay cells and amplifiers are implemented as differential structures, in the output V4, the sum of harmonic factors of an even order is `0`, and harmonic factors of an odd order remain. The 3rd order harmonic factor is largest among harmonic factors of an odd order, so the frequency of the output V4 becomes the oscillation frequency of the ring oscillator, namely 3 times frequency of a fundamental one and V4 is same as the oscillation frequency of 1 stage ring oscillator shown in FIG. 1B. The signal amplitude of harmonic factors is so small comparing with that of fundamental factors, because outputs of the ring oscillator operated in a high speed are nearly sinusoidal waves.
Eventually, the signal amplitude of outputs Vx is as small as tens or less mV. In PLL the oscillator's output operates other circuits such as mixer, but it is impossible that this signal operates well other circuits in a high frequency region. However in bipolar circuits, it is operated stably with tens of mV signals, so pseudo 1 stage ring oscillator shown in FIG. 1B is suitable not for CMOS only for bipolar circuits. In a real implementation to bipolar circuits, it is also used the method that the common base amplifier is added to the pre-stage of the load resistor (141) in order that it has harmonic factors increased.
FIG. 2 is a circuit diagram of a conventional frequency-quadrupling ring oscillator.
The circuit is composed of differential delay cells (210, 220, 230, 240) and differential mixers (250, 260, 270). If a ring oscillator has even numbers of stages, quadrature signals which have 90 degrees of phase difference exist among output signals.
For example, outputs V211 and V231, V221 and V241 are quadrature signals each other, and differential signals "V211-V212" and "V231-V232", "V221-V222" and "V241-V242" are also quadrature ones each other. Mixers (250, 260, 270) receive two differential signals of quadrature as inputs. Because mixer operates like a real analog multiplier, when two signals which are quadrature are multiplied each other, the frequency of a mixer is two times of input signal's frequency, so output voltages V252 and V271 of mixers (250, 270) are two times of ring oscillation frequency and quadrature each other at the same time.
Hence, outputs V261 and V262 of the mixer (260) which receive above two signals as inputs are four times of a ring oscillation frequency. The mixer circuit is implemented as in the form of Gilbert multiplier. In this case, mixers (250, 270) must operate in speed of 2 times of a ring frequency, the mixer (260) must operate in speed of 4 times.
Thus, it is impossible that the mixer circuit which operate in a high speed is implemented with CMOS. After all, the frequency-quadrupling ring oscillator is also not suitable for CMOS circuits.
Until now, we did examine methods that the high speed PLL is implemented in detail in many points of view. As described above, conventional structures of the ring oscillator which makes a oscillation frequency heightened are not suitable that implemented as CMOS circuits, so the new design of structure is required and the proper delay cell must be improved.